During conventional semiconductor processing, plasma techniques are routinely employed, particularly in manufacturing Very Large Scale Integrated (VLSI) devices. Such conventional plasma techniques comprise etching various films, including polycrystalline silicon, oxides and metals. Plasma techniques are also conventionally employed for oxide deposition, sputter pre-clean prior to physical vapor deposition, photoresist stripping and during ion implantation. During such plasma processing, devices fabricated on silicon wafers are usually directly exposed to the plasma. Such plasma exposure is known to cause degradation of the gate dielectric layer, such as silicon oxide, e.g., silicon dioxide, in MOS devices attributed to electrical charging during the plasma process.
In the plasma ambient, metal or polycrystalline silicon electrodes serve as antennas, thereby collecting ions and electrons during plasma processing. A steady state voltage appears on the electrode due to charge collection and the resulting electrical stress is capable of destroying the underlying gate electrode by oxide breakdown or weakening it by causing charge trapping in the oxide as well as interface trap generation at the silicon dioxide-silicon interface. Since the damaged oxide may cause IC yield loss or become more vulnerable to hot-carrier induced degradation and time-dependent dielectric breakdown, plasma-induced gate oxide degradation constitutes a serious problem in VLSI technology. See, for example, Zheng et al., "A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient," 1996 1st International Symposium on Plasma Process-Induced Damage (IEEE Cat. No. 96TH8142), 1996, pp. 27-29; H. C. Shin et al., "Thin gate oxide damage due to plasma processing," Semiconductor Science and Technology, April 1996, Vol. 11, No. 4, pp. 463-473; H. Shin et al., "Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide," International Electron Devices Meeting 1993, IEEE Cat. No. 93CH3361-03, 1993, pp. 467-470; and M. C. Chang et al., "Degradation of MOS Transistor Characteristics by Gate Charging Damage During Plasma Processing," International Symposium on VLSI Technology, Systems, and Applications, IEEE Cat. No. 93TH0524-9, 1993, pp. 320-324.
As integration increases and the feature size for devices decrease, the thickness of gate oxide layers decreases, thereby exacerbating the adverse impact of plasma charging damage. A conventional approach to the plasma charging damage problem comprises the formation of a protection diode to which the polycrystalline silicon layer, i.e., gate electrode/word line, is connected, thereby providing a discharge path for electrical charging during plasma processing.
Conventional practices with respect to a protection diode are attendant with numerous disadvantages, particularly in requiring extra layout area, thereby increasing the total die size and hindering miniaturization. As a result of the consequential increase in precious chip real estate, protection diodes are sparingly used, being reserved for only the most critical areas of the circuit, typically devices connected to bond pads. Copending application Ser. No. 08/798,993, filed Feb. 11, 1997, discloses a self-aligned protection diode which is formed at the first polycrystalline silicon level with a reduced layout area.
As design features shrink to smaller and smaller dimensions, it becomes increasingly more significant to quantify the degree of damage to the transistor gate dielectric layer, e.g., silicon dioxide, applicable to real circuit operating conditions, and to indicate which process steps are most damaging. One such technique is disclosed by R. Rakkhit et al., "PROCESS INDUCED OXIDE DAMAGE AND ITS IMPLICATIONS TO DEVICE RELIABILITY OF SUBMICRON TRANSISTORS," IEEE/IRPS 1993, pp. 293-296, and comprises assessing plasma induced gate dielectric damage by a "Vt-Fluence" testing technique. Vt-Fluence testing comprises the application of a constant gate current forced through the gate oxide in the Fowler-Nordheim tunneling regime for 200 seconds. The threshold voltage of the transistor is monitored periodically during the stress.
As densification increases and geometries shrink to 0.25 microns and under, e.g., 0.18 microns, the thickness of gate dielectric layers shrink to under 50 .ANG., e.g., under 40 .ANG.. Moreover, as gate dielectric layers shrink to below 50 .ANG. in thickness, the operative mechanism is no longer Fowler-Nordheim, but direct tunneling. The Vt-Fluence technique is not sensitive to detecting plasma induced damage in such ultra thin gate dielectric layers, because the leakage current becomes larger and larger due to direct tunneling vis-a-vis Fowler-Nordheim tunneling. A high field across the gate oxide does not occur with direct tunneling, since charges c an tunnel through the gate oxide at a lower field and, hence, less damage is induced due to direct tunneling. Thus, the Vt-Fluence testing method, which essentially monitors MOSFET device threshold voltage shifts due to Fowler-Nordheim tunneling, is not sensitive to significant smaller damage induced by direct tunneling.
Accordingly, there exists a need to develop a method of assessing plasma induced degradation of an ultra thin gate dielectric layer. There also exists a need to develop as to a method of determining which of various plasma processing step s during semiconductor manufacturing are most damaging in terms of gate dielectric degradation.